Semiconductor device performance is influenced by the uniformity of the line width of the transistor gate. A rough line can lead to yield loss. Control of the line width roughness (LWR) is thus a critical issue in lithography, even more so when line widths approach tens of nanometers.
LWR occurs even if the projected image on the photoresist is perfectly smooth. It is caused by the material properties of the resist, post-lithography processing steps and shot noise. The latter is related to the statistical behaviour of the irradiating particles that land on the resist. Statistical influences can generally be reduced by sampling over longer periods. However, if we extend the illumination time, the waferstepper throughput decreases. Researching the influences on the LWR is therefore crucial.
Even when the resist properties, the projected image and the shot noise statistics are kept the same, many other factors influence the LWR: the measurement itself and the way the lines are printed. The major challenge lies in isolating the relevant LWR influence from the measurement method and the printing method. For this purpose, we automatically calculated the correlation between tens of thousands of SEM images. The influence of fundamental physical processes is studied using computer simulations.
Finding resists with good sensitivity, good resolution and low LWR is considered to be top priority for EUV lithography. Theoretical models of resists help us to develop promising materials for the semiconductor industry.